1. Field of the Invention
The present invention relates generally to comparator systems.
2. Description of the Related Art
On-going developments in photolithographic and electron-beam lithographic processes have realized successively smaller dimensions for integrated-circuit interconnect structures. Although these reduced structures have facilitated an impressive increase in the package density of integrated-circuit components (e.g., logic gates), they have also limited the supply voltage (generally indicated by Vdd for metal-oxide-semiconductor (MOS) transistors and by Vcc for bipolar junction transistors) that can be applied to bias these components. The limited supply voltages (e.g., 3.3 volts) are primarily for protection of MOS gate structures but the same limitations are imposed on the design of all components in combined-technology integrated circuits, e.g., those that combine MOS and bipolar junction devices.
In every electronic circuit, the available supply voltage must be divided between component headroom (minimum voltage needed for device operation) and dynamic range (difference between least and greatest processed signals). The more headroom a given circuit design requires, the less dynamic range it can provide. In particular, conventional differential comparator structures (e.g., as in flash analog-to-digital converters) have typically required substantial headroom and, accordingly, their dynamic range has suffered as the available supply voltage has declined.
The present invention is directed to differential comparator systems that substantially enhance comparator dynamic range.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.